1. Field of the Invention
The present invention relates to integrated circuit elements and, in particular, to a merged single polysilicon bipolar NPN transistor that, instead of utilizing separate isolation islands for emitter-base and collector contacts, utilizes a single isolation island, thereby significantly reducing device area.
2. Discussion of the Related Art
Conventional bipolar NPN transistors require two separate active areas: one for the main device, i.e. the vertical emitter-base-collector NPN junctions, and another for the sink contact to the NPN collector. For many fabrication technologies, implementation of these two areas requires a significant amount of silicon area because the isolation processes used in these technologies cannot readily be scaled. For example, in some technologies, if the spacing between isolation islands is reduced to too small a distance, then the field oxide does not grow properly, resulting in silicon crystal defects.
Other types of isolation processing, such as deep trench isolation, can greatly reduce device area, but are very complex.
FIGS. 1A-1E show a general process flow for fabricating a conventional vertical bipolar NPN transistor. FIG. 1A shows an N+ buried layer 102 formed in a silicon substrate 100. Field oxide isolation regions 104, including a separate oxide isolation region 104', define two separate active regions: an N- region 106 in which the vertical emitter-base-collector junctions of the main NPN device will be formed and an N+ region 108 which serves as the sink contact to the NPN collector.
Referring to FIG. 1B, following deposition of a layer 110 of polysilicon, a base implant mask is defined to expose the poly layer 110 above the N- active region 106. P-type dopant is then implanted into the exposed portions of the poly layer 110, the dopant is outdiffused from the poly layer 110 into the underlying N- active region 106 in a thermal step, and the structure is annealed to form P- base region 112. The base mask is then stripped and N+ and P+ poly implant modules are sequentially performed (the order is not critical), resulting in the structure shown in FIG. 1B.
Referring to FIG. 1C, the poly layer 110 is then masked and etched to defined raised P+ poly base contact region 114, N+ poly emitter region 116 and N+ poly sink contact region 118. A thermal drive-in step is then performed to diffuse N-type dopant from N+ poly emitter region 116 into base region 112 to form emitter contact 120.
As shown in FIG. 1D, following a masked link base implant, a layer of spacer oxide is deposited and etched back to form oxide sidewall spacers 122 on the poly regions 114, 116 and 118. A P+ implant is then performed to complete the extrinsic base regions. A final anneal step is then performed to activate the dopants and salicide contact layers 124 are provided, resulting in the structure shown in FIG. 1E.